发明名称 Bump structural designs to minimize package defects
摘要 The mechanisms for forming bump structures enable forming bump structures between a chip and a substrate eliminating or reducing the risk of solder shorting, flux residue and voids in underfill. A lower limit can be established for aαratio, defined by dividing the total height of copper posts in a bonded bump structure divided by the standoff of the bonded bump structure, to avoid shorting. A lower limit may also be established for standoff the chip package to avoid flux residue and underfill void formation. Further, aspect ratio of a copper post bump has a lower limit to avoid insufficient standoff and a higher limit due to manufacturing process limitation. By following proper bump design and process guidelines, yield and reliability of chip packages may be increases.
申请公布号 US8698308(B2) 申请公布日期 2014.04.15
申请号 US201213362913 申请日期 2012.01.31
申请人 LIN JING-CHENG;HUANG CHENG-LIN;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 LIN JING-CHENG;HUANG CHENG-LIN
分类号 H01L29/40 主分类号 H01L29/40
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