发明名称 |
SYSTEM AND METHOD FOR BUILT-IN SELF TEST (BIST) IN AN INTEGRATED CIRCUIT |
摘要 |
Embodiments of the disclosure relate to a method and system for Built-in-Self- Test of analog signals with minimal area overhead, for measuring on-chip voltages in an all-digital manner. The method is well suited for a distributed architecture, where the routing of analog signals over long paths is minimized. A clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head, present at each test node, which consists of a pair of delay cells and a pair of flip-flops, locally converts the test voltage to a skew between a pair of sub-sampled signals, thus giving rise to as many sub-sampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding sub-sampled signal pair is fed to a Delay Measurement Unit (DMU) to measure the skew between this pair. |
申请公布号 |
WO2014049402(A1) |
申请公布日期 |
2014.04.03 |
申请号 |
WO2012IB57462 |
申请日期 |
2012.12.19 |
申请人 |
DEPARTMENT OF ELECTRONICS AND INFORMATION TECHNOLOGY;INDIAN INSTITUTE OF SCIENCE |
发明人 |
VASUDEVAMURTHY, RAJATH;AMRUTUR, BHARADWAJ |
分类号 |
G01R31/3187;G01R19/00;G01R31/3167 |
主分类号 |
G01R31/3187 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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