发明名称 MULTI-BIT RESISTANCE MEASUREMENT
摘要 An example embodiment is a circuit for determining a binary value of a memory cell. The circuit includes shunt capacitors having different capacitances to selectively couple with the memory cell, and a controller configured to iteratively charge the shunt capacitors to a first voltage until a selected shunt capacitor causes the first voltage to decay through the memory cell to a first reference voltage within a predetermined time range, determine a binary value of the most significant bits of the memory cell based on the selected shunt capacitor, charge the selected shunt capacitor to a second voltage after determining the binary value of the most significant bits of the memory cell, and determine a binary value of the least significant bits of the memory cell based on a decay of the second voltage at the selected shunt capacitor through the memory cell.
申请公布号 US2014092694(A1) 申请公布日期 2014.04.03
申请号 US201213584120 申请日期 2012.10.28
申请人 LAM CHUNG H.;LI JING;MONTOYE ROBERT K.;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 LAM CHUNG H.;LI JING;MONTOYE ROBERT K.
分类号 G11C7/00 主分类号 G11C7/00
代理机构 代理人
主权项
地址