| 摘要 |
The multi-dimensional data registration integrated circuit for driving array-arrangement devices, comprising: a plurality of the i-th hierarchy sets, each of the i-th hierarchy sets is divided into a plurality of the (i+1)-th hierarchy sets; a i-th hierarchy address selection circuit, comprising a signal generation unit and a multiplexing unit, wherein the former generates an enable signal, the latter is connected to the signal generating unit and shifts the input data based on the enable signal and a second timing signal to further generate n bits of address signals, the i-th hierarchy address selection circuit is used to scan the plurality of the i-th hierarchy sets and select at least one of the i-th hierarchy sets to function; and a data supply circuit to follow a scan sequence of a j-th hierarchy address selection circuit and write a plurality of data into the selected j-th hierarchy sets. |
