METHOD FOR TESTING BROADSIDE PATH DELAY FAULT OF DIGITAL COMBINATION INTEGRATED CIRCUIT

摘要

A method for testing a broadside path delay fault of a digital combination integrated circuit, comprising: determining a testable path circuit; selecting some test paths from the testable path circuit to generate a test path set; obtaining at least one first test path having most fan-outs, calculating an influence cone and a test vector thereof; selecting a labeled path having a minimum overlap ratio with the influence cone; determining whether the labeled path meets a compression requirement; if yes, compressing the labeled path to obtain a test pair thereof and updating the test vector thereof according to the test pair to obtain a final test vector; repeating above steps until there is no test path in the test path set to obtain a final test vector set; and performing a fault simulation according to the final test vector set on the testable path circuit to detect a fault path.