| 摘要 |
<p>There is provided a level shift circuit that does not affect delay time, regardless of the size of resistor resistance value. A level shift circuit of the invention includes first and second series circuits (221 and 222) wherein first and second resistors (Rpar1 and Rpar2) and first and second switching elements (HVN1 and HVN2) are connected in series, rise detector circuits (321 and 322) that compare the rise potentials of output signals of the first and second series circuits with a predetermined threshold value, and output first and second output signals, which are pulse outputs of a constant duration, when the threshold value is exceeded, and third and fourth switching elements (PM1 and PM2) connected in parallel to the first and second resistors respectively. The gate terminals of the third and fourth switching elements are connected to the rise detector circuits, and the third and fourth switching elements are turned on by the first and second output signals respectively.</p> |
