发明名称 Method and system for reducing triggering latency in universal serial bus data acquisition
摘要 A method of controlling one or more devices in data communication with a common controller to perform one or more functions, each of the devices having a synchronous clock, a synchronized real time clock register and a memory, the method comprising: arming the devices such that the devices commence performing the functions synchronously, receive and store to their respective memory data acquired as a result of performing the functions and store to their respective memory time stamp information indicative of the time of acquisition of the acquired data; a trigger device in data communication with the common controller responding to a command to perform the functions by sending a first message to the host controller that includes data indicative of a time of receipt of the command; the host controller responding to the first message by sending the devices a second message including data indicative of the time of receipt by the further device of the command; and the devices responding to the second message by reading their respective memories and sending the acquired data stored therein to the host controller commencing from a location in each respective memory corresponding to the time of receipt or a next available location.
申请公布号 US8688874(B2) 申请公布日期 2014.04.01
申请号 US20080527822 申请日期 2008.05.12
申请人 FOSTER PETER;CHRONOLOGIC PTY. LTD. 发明人 FOSTER PETER
分类号 G06F3/00;G06F5/00 主分类号 G06F3/00
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