发明名称 ESD Clamp in Integrated Circuits
摘要 A device includes a High-Voltage N-Well (HVNW) region have a first edge, and a High-Voltage P-Well (HVPW) region having a second edge adjoining the first edge. A first Shallow N-well (SHN) region is disposed over a lower portion of the HVNW region, wherein the first SHN region is spaced apart from the first edge by an upper part of the HVNW region. A second SHN region is disposed over a lower portion of the HVPW region, wherein the second SHN region is laterally spaced apart from the second edge. A Shallow P-well (SHP) region is disposed over the lower portion of the HVPW region, and is between the first SHN region and the second SHN region. The SHP region has a p-type impurity concentration higher than a p-type impurity concentration of the HVPW region. An isolation region is disposed over and contacting the SHP region.
申请公布号 US2014084373(A1) 申请公布日期 2014.03.27
申请号 US201213624701 申请日期 2012.09.21
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 HUANG CHIEN-FU
分类号 H01L23/62 主分类号 H01L23/62
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