| 摘要 |
A stacked package includes a first package substrate having a major surface that defines a horizontal plane, first pads on an upper portion of the first package substrate, a multilayer capacitor on the first pads, and a first semiconductor chip on the first package substrate. A second package substrate is provided on the first semiconductor package, and a second semiconductor chip is on the second package substrate. Conductive bumps are provided between the first package substrate and the second package substrate that are vertically aligned with the multilayer capacitor. Signal characteristics in the stacked package may be improved by the multilayer capacitor. Because the multilayer capacitor is formed in the stacked package it may provide for an increased degree of integration. |
