| 摘要 |
<p>A programmable logic device and validation method thereof are provided that are capable of efficiently validating whether the internal state shown by a sequential circuit transitions equivalently to a logic program in a hardware description language (HDL). This programmable logic device (10) is provided with: an I/O unit (17) which inputs and outputs digital signals to and from mounted logic elements and externally; generation units (12 (12a, 12b, 12c, 12d)) which acquire an internal state signal of the sequential circuits included in sub-regions (11 (11a, 11b, 11c, 11d)) into which a group of logic elements has been divided, and generates state information (13 (13a, 13b, 13c, 13d)) by sub-region (11) units; and a selection output unit (14) which acquires the state information (13) from each of the sub-regions (11) and selectively outputs the same externally.</p> |
