FABRICATING A SEMICONDUCTOR DIE HAVING COEFFICIENT OF THERMAL EXPANSION GRADED LAYER

摘要

A method of fabricating a semiconductor die includes circuit elements configured to provide a circuit function. A substrate including a bottomside and a topside is provided. At least one multi-layer structure is formed. The forming is done by depositing a coefficient of thermal expansion (CTE) graded layer comprising at least a dielectric portion on a first material having a first CTE to provide a first side facing said first material and a second side opposite the first side. The depositing includes flowing a first reactive component and at least a second reactive component. A gas flow ratio of the first reactive component relative to the second reactive component is automatically changed during a deposition time to provide a non-constant composition profile which has a graded CTE that increases from the first side to the second side. A metal layer comprising a second material having a second CTE is formed on the second side. The second CTE is higher than the first CTE.