发明名称 |
Optimal channel design for memory devices for providing a high-speed memory interface |
摘要 |
A system is provided for high-speed communication between a memory controller and a plurality of memory devices. A memory controller, and a plurality of memory devices are provided. Additionally, at least one channel is included for providing electrical communication between the memory controller and the plurality of memory devices, an impedance of the channel being at least partially controlled using High Density Interconnect (HDI) technology. |
申请公布号 |
US8675429(B1) |
申请公布日期 |
2014.03.18 |
申请号 |
US201213597895 |
申请日期 |
2012.08.29 |
申请人 |
WANG MIN;FEROLITO PHILIP ARNOLD;RAJAN SURESH NATARAJAN;SMITH MICHAEL JOHN SEBASTIAN;GOOGLE INC. |
发明人 |
WANG MIN;FEROLITO PHILIP ARNOLD;RAJAN SURESH NATARAJAN;SMITH MICHAEL JOHN SEBASTIAN |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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