发明名称 Cache memory control apparatus and cache memory control method
摘要 According to an aspect of the embodiment, an FP includes a plurality of entries which holds requests to be processed, and each of the plurality of entries includes a requested flag indicating that data transfer is once requested. An FP-TOQ holds information indicating an entry holding the oldest request. A data transfer request prevention determination circuit checks the requested flag of a request to be processed and the FP-TOQ, and when a transfer request of data as a target of the request to be processed has already been issued and the entry holding the request to be processed is not the entry indicated by the FP-TOQ, transmits a signal which prevents the transfer request of the data to a data transfer request control circuit. Even when a cache miss occurs in a primary cache RAM, the data transfer request control circuit does not issue a data transfer request when the signal which prevents the transfer request is received.
申请公布号 US8677070(B2) 申请公布日期 2014.03.18
申请号 US20090654312 申请日期 2009.12.16
申请人 KIYOTA NAOHIRO;FUJITSU LIMITED 发明人 KIYOTA NAOHIRO
分类号 G06F12/00 主分类号 G06F12/00
代理机构 代理人
主权项
地址