| 摘要 |
The present invention relates to an equalizer to equalize the phase and frequency used in a serial data receiver. According to the present invention, provided is an equalizer which comprises: a phase locked loop; a frequency comparer for comparing a reference clock with an input clock recovered from input data; and a PLL distribution controller for outputting the demultiply ratio of the phase locked loop using a comparison value inputted by the frequency comparer. The phase locked loop demultiplies an output frequency based on the demultiply ratio using the output signal of the PLL distribution controller. [Reference numerals] (AA) Click data; (BB) Frequency comparer; (CC) PLL distribution controller; (DD) Frequency phase detector; (EE) Loop filter; (FF) Voltage control generator; (GG) Phase interpolator; (HH) 1/N divider; (II) 1/a divider |
