| 摘要 |
1,153,462. Semi-conductor devices. MULLARD Ltd. 22 June, 1966 [22 June, 1965; 26 June, 1966], Nos. 26340/65 and 27846/66. Heading H1K. In a semi-conductor device having a conductive track overlying an insulating layer, an unwanted channel formed beneath the conductor is interrupted by increasing the conductivity of part of the underlying region. In a first embodiment, Figs. 1 to 3 (not shown), an IGFET is produced by masking an N-type silicon wafer with silicon oxide or silicon nitride, using a photolithographic technique and diffusing-in boron to form interdigitated P-type source and drain regions (4, 5) and to form a separate P-type region (3) which provides a protective diode. The wafer is remasked and phosphorus is diffused-in to form a region (6) more heavily doped than the remainder of the substrate. The masking material is removed and replaced with clean silicon oxide, apertures are formed to expose parts of the source and drain regions (4, 5) and part of the diode region (3), and a layer of aluminium is vapour deposited on the surface and etched to form source and drain contacts (8, 9) and a gate conductor (7) which overlies the interdigitated parts of the source and drain regions and contacts the diode region (3). The diode is arranged so that it conducts before sufficient voltage is applied to the gate conductor to break down the insulation. The more heavily doped region (6) of the substrate underlies part of the gate conductor between the source region (5) and the diode region (3) to interrupt the unwanted channel which is formed in use between these regions. In a second embodiment, Figs. 4 to 6 (not shown), a pair of NPN junction transistors is formed in an N-type wafer (40) which forms a common collector region, by diffusing-in separate base and emitter regions (35, 36; 37, 38). A more heavily doped N-type region (50) is diffused into the substrate between the base regions (35, 36) simultaneously with the emitter diffusion, and conductive tracks are provided over an insulating layer to connect the transistors in the form of a " Darlington pair." The connection (48) between the emitter region (37) of the first transistor and the base region (36) of the second transistor passes over the more heavily doped region (50) of the substrate which interrupts the channel formed under this conductor in operation which would otherwise form a leakage path between the base regions of the transistors. In a third embodiment, Figs. 7 to 9 (not shown), a pair of complementary insulated gate FET's produced as described in Specification 1,153,463 have their gate conductors extended to a common connecting point. The extended part of one of the gate conductors crosses a more highly doped region of the substrate which interrupts the channel which forms beneath the extended parts of the gate conductors. |
