| 摘要 |
The present invention relates to an integrated circuit including a plurality of semiconductor memory devices which are stacked to have a stack structure. The integrated circuit includes the semiconductor memory device which includes a decoding unit for generating a plurality of mode register setting codes by decoding an input address when a mode register is set and a decoding operation control unit for controlling the operation of the decoding unit to output a decoding result as a preliminary code or an additional mode register setting code in response to a stack signal if the value of the input address is equal to a preset value. It is determined whether or not the stack signal is activated according to whether or not the semiconductor memory devices are stacked. [Reference numerals] (200,210) MRS setting block; (220,230) AL decoder |
