发明名称 BUMPLESS BUILD-UP LAYER PACKAGE WARPAGE REDUCTION
摘要 The present disclosure relates to the field of fabricating microelectronic packages and the fabrication thereof, wherein a microelectronic device may be formed within a bumpless build-up layer coreless (BBUL-C) microelectronic package and wherein a warpage control structure may be disposed on a back surface of the microelectronic device. The warpage control structure may be a layered structure comprising at least one layer of high coefficient of thermal expansion material, including but not limited to a filled epoxy material, and at least one high elastic modulus material layer, such as a metal layer.
申请公布号 KR20140026570(A) 申请公布日期 2014.03.05
申请号 KR20137034216 申请日期 2012.06.29
申请人 INTEL CORP. 发明人 MALATKAR PRAMOD;DELANEY DREW W.
分类号 H01L23/48;H01L23/12 主分类号 H01L23/48
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