发明名称 |
Functional unit for vector integer multiply add instruction |
摘要 |
A vector functional unit implemented on a semiconductor chip to perform vector operations of dimension N is described. The vector functional unit includes N functional units. Each of the N functional units have logic circuitry to perform: a first integer multiply add instruction that presents highest ordered bits but not lowest ordered bits of a first integer multiply add calculation, and, a second integer multiply add instruction that presents lowest ordered bits but not highest ordered bits of a second integer multiply add calculation. |
申请公布号 |
US8667042(B2) |
申请公布日期 |
2014.03.04 |
申请号 |
US20100890497 |
申请日期 |
2010.09.24 |
申请人 |
WIEDEMEIER JEFF;SAMUDRALA SRIDHAR;GOLLIVER ROGER;INTEL CORPORATION |
发明人 |
WIEDEMEIER JEFF;SAMUDRALA SRIDHAR;GOLLIVER ROGER |
分类号 |
G06F7/38;G06F15/00;G06F15/76 |
主分类号 |
G06F7/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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