发明名称 Polishing estimation/evaluation device, overpolishing condition calculation device, and computer-readable non-transitory medium thereof
摘要 A polishing estimation/evaluation device includes a dividing unit, an overpolished area extracting unit, and a dummy modifying unit. The dividing unit divides a layout of an integrated circuit into a plurality of partial areas. The overpolished area extracting unit refers to an overpolishing condition indicating whether overpolishing occurs in a vicinity of a partial area based on a wiring density in the partial area and a wiring density in surrounding areas of the partial area, and extracts a partial area where the overpolishing occurs from the plurality of partial areas obtained by the division by the dividing unit. The dummy modifying unit modifies dummy wiring in the partial area where the overpolishing occurs extracted by the overpolished area extracting unit and/or dummy wiring in surrounding areas of the partial area to reduce the number of partial areas where the overpolishing occurs.
申请公布号 US8667433(B2) 申请公布日期 2014.03.04
申请号 US201213593558 申请日期 2012.08.24
申请人 FUKUDA DAISUKE;FUJITSU LIMITED 发明人 FUKUDA DAISUKE
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项
地址