发明名称 |
Concurrent placement and routing using hierarchical constraints |
摘要 |
An automated layout method allows designing advanced integrated circuits with design rules of high complexity. In particular, a hierarchical constrained layout process is applicable and useful for analog and mixed-signal integrated circuit designs and may be based on an incremental concurrent placement and routing. Use of constraints from multiple levels of a circuit description hierarchy allows computationally efficient processing of logical circuit increments and produces high-quality outcomes. Users such as circuit designers can exercise a high degree of predictability and control over the resulting physical layout construction by either user-specified or computer-generated constraints. |
申请公布号 |
US8667444(B2) |
申请公布日期 |
2014.03.04 |
申请号 |
US201213399803 |
申请日期 |
2012.02.17 |
申请人 |
HENRICKSON LINDOR E.;LIM LYNDON C.;SYNOPSYS, INC. |
发明人 |
HENRICKSON LINDOR E.;LIM LYNDON C. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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