发明名称 |
Discrimination phase margin monitor circuit, transmitting/receiving device and communication system |
摘要 |
<p>The discrimination phase margin monitor circuit (10) of the present invention comprises a first discrimination circuit (11 and 12) discriminating an input data signal using a clock signal extracted from the input data signal, a second discrimination circuit (13 and 14) discriminating the input data signal using a clock signal with a frequency different from that of the clock and an operation circuit (15 and 16) calculating the exclusive OR of the output signal of the first discrimination circuit and that of the second discrimination circuit and obtaining a phase margin monitor output signal by averaging the exclusive ORs.</p> |
申请公布号 |
EP1583307(B1) |
申请公布日期 |
2014.02.26 |
申请号 |
EP20040022479 |
申请日期 |
2004.09.22 |
申请人 |
FUJITSU LIMITED |
发明人 |
KUWATA, NAOKI |
分类号 |
H04L25/02;H04L25/06;H04B10/07;H04B10/25;H04B10/2507;H04B10/524;H04B10/58;H04J14/02;H04L7/02;H04L7/033;H04L25/03 |
主分类号 |
H04L25/02 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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