ERASE FOR 3D NON-VOLATILE MEMORY WITH SEQUENTIAL SELECTION OF WORD LINES
摘要
An erase operation for a 3D stacked memory device adjusts a start time of an erase period and/or a duration of the erase period for each storage element based on a position of the storage element. A voltage is applied to one or both drive ends of a NAND string to pre-charge a channel to a level which is sufficient to create gate-induced drain leakage at the select gate transistors. With timing based on a storage element's distance from the driven end, the control gate voltage is lowered to encourage tunneling of holes into a charge trapping layer in the erase period. The lowered control gate voltage results in a channel-to-control gate voltage which is sufficiently high to encourage tunneling. The duration of the erase period is also increased when the distance from the driven end is greater. As a result, a narrow erase distribution can be achieved.
申请公布号
WO2014028308(A1)
申请公布日期
2014.02.20
申请号
WO2013US54232
申请日期
2013.08.09
申请人
SANDISK TECHNOLOGIES, INC.
发明人
COSTA, XIYING;YU, SEUNG;SCHEUERLEIN, ROY, E.;LI, HAIBO;MUI, MAN, L.