发明名称 |
CUSTOM CHAINING STUBS FOR INSTRUCTION CODE TRANSLATION |
摘要 |
A processing system includes a microprocessor, a hardware decoder arranged within the microprocessor, and a translator operatively coupled to the microprocessor. The hardware decoder is configured to decode instruction code non-native to the microprocessor for execution in the microprocessor. The translator is configured to form a translation of the instruction code in an instruction set native to the microprocessor and to connect a branch instruction in the translation to a chaining stub. The chaining stub is configured to selectively cause additional instruction code at a target address of the branch instruction to be received in the hardware decoder without causing the processing system to search for a translation of additional instruction code at the target address. |
申请公布号 |
US2014052962(A1) |
申请公布日期 |
2014.02.20 |
申请号 |
US201213586700 |
申请日期 |
2012.08.15 |
申请人 |
HERTZBERG BEN;TUCK NATHAN;NVIDIA CORPORATION |
发明人 |
HERTZBERG BEN;TUCK NATHAN |
分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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