| 摘要 |
The present invention relates to a semiconductor memory device and an operating method of the same which comprises: a memory cell array including even cell strings, which are connected in between a first common source line and even bit lines and contain a plurality of memory cells, and odd cell strings, which are connected in between a second common source line and odd bit lines and contain a plurality of memory cells; and peripheral circuits in order to apply a positive voltage to the second common source line during a read operation of the even cell strings, and to apply the positive voltage to the first common source line during a read operation of the odd cell strings. [Reference numerals] (120) Control circuit; (130) Voltage generating circuit; (140) Row decoder; (160) Column selection circuit; (170) Input/output circuit; (180) Pass/fail judgment circuit |
