| 摘要 |
A shift register is provided. In the shift register, each of successively cascaded shift register units includes first and second switches and first and second capacitors. For the first switch, a control terminal is coupled to a first node, an input terminal receives a first clock signal, and an output terminal is coupled to an output node. The first capacitor is coupled between the first node and the output node. The second capacitor is coupled between the output node and a ground terminal. For the second switch, an input terminal receives a second clock signal, and an output terminal is coupled to the first node. A carry signal is generated at the first node. For the N-th shift register unit, a control terminal of the second switch receives the carry signal generated at the first node of the previous shift register unit. |
