发明名称 Delay block for controlling a dead time of a switching voltage regulator
摘要 Embodiments for at least one method and apparatus for controlling timing of switch control signals of a switching voltage regulator disclosed. One method includes generating a regulated output voltage based upon a switching voltage, generating the switching voltage through controlled closing and opening of a series switch element and a shunt switch element, and controlling, by a delay block, the closing and opening of the series switch element and a shunt switch element. The delay block control includes receiving, by the delay block, a timing signal, generating a one of a series switch control signal and a shunt switch control signal by controllably delaying the timing signal with a first delay, and generating one other of the series switch control signal and the shunt switch control signal by inverting, and controllably delaying the timing signal with a second delay.
申请公布号 US8648583(B2) 申请公布日期 2014.02.11
申请号 US201113225434 申请日期 2011.09.03
申请人 BROWN JAMES E. C.;ROTHENBERG BRET;R2 SEMICONDUCTOR, INC. 发明人 BROWN JAMES E. C.;ROTHENBERG BRET
分类号 G05F1/00;H03K4/90;H03L7/06 主分类号 G05F1/00
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