发明名称 PARASITIC CAPACITANCE REDUCTION CIRCUIT FOR ELECTRONIC DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a parasitic capacitance reduction circuit for an electronic device which reduces a parasitic capacitance formed in a circuit on a printed board and implements a stable operation of the circuit.SOLUTION: The parasitic capacitance reduction circuit for an electronic device formed by elements disposed on a printed board and configured to handle a signal of a predetermined frequency or a bandwidth of signals centered at the predetermined frequency includes inductance sections Lp1, Lp2 connected in parallel with parasitic capacitances Cp1, Cp2 formed by the disposition of the elements on the printed board, and including inductance elements. Coils Lp11, Lp21 of the inductance sections Lp1, Lp2 form with the parasitic capacitances Cp1, Cp2 parallel resonance circuits adapted to resonate at the predetermined frequency.
申请公布号 JP2014017711(A) 申请公布日期 2014.01.30
申请号 JP20120154576 申请日期 2012.07.10
申请人 JAPAN RADIO CO LTD 发明人 AKAHORI KOICHIRO
分类号 H03B5/12 主分类号 H03B5/12
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