发明名称 |
VERIFICATION FOR FUNCTIONAL INDEPENDENCE OF LOGIC DESIGNS THAT USE REDUNDANT REPRESENTATION |
摘要 |
Computer-implemented techniques are disclosed for verifying functional independence of logic designs that make use of redundant representations. Initially, the design of a logic component is obtained. Two representations of the component are computed, one in redundant form and another in non-redundant form. A randomness factor based on a time-varying value is injected into the second representation. The value from the second form is then constrained to the context of the logic component within a digital system. It is then possible to analyze the component using the first deterministic representation and the constrained second representation. This analysis allows verification of the component with downstream logic. |
申请公布号 |
US2014033147(A1) |
申请公布日期 |
2014.01.30 |
申请号 |
US201213561000 |
申请日期 |
2012.07.28 |
申请人 |
SHAO YUN;TENCA ALEXANDRE FERREIRA |
发明人 |
SHAO YUN;TENCA ALEXANDRE FERREIRA |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|