发明名称 TFET based 4T memory devices
摘要 A four transistor (4T) memory device is provided. The device includes a first cell transistor and a second cell transistor, the first and second cell transistors coupled to each other and defining latch circuitry having at least one multi-stable node. The device further includes a first access transistor and a second access transistor, the first and second access transistors coupling the at least one multi-stable node to at least one bit-line. In the device, each of the first and second cell transistors and each of the first and second access transistors is a unidirectional field effect transistor configured for conducting current in a first direction and to be insubstantially incapable of conducting current in a second direction.
申请公布号 US8638591(B2) 申请公布日期 2014.01.28
申请号 US201113153027 申请日期 2011.06.03
申请人 SARIPALLI VINAY;MOHATA DHEERAJ;MOOKHERJEA SAURABH;DATTA SUMAN;NARAYANAN VIJAYKRISHNAN;THE PENN STATE RESEARCH FOUNDATION 发明人 SARIPALLI VINAY;MOHATA DHEERAJ;MOOKHERJEA SAURABH;DATTA SUMAN;NARAYANAN VIJAYKRISHNAN
分类号 G11C5/06;G11C11/41;G11C11/412 主分类号 G11C5/06
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