| 摘要 |
A phase detector demodulates a carrier wave which is modulated by a phase shift keying (PSK), a quadrature amplitude modulation, or a similar digital modulated wave. The detector detects the phase difference between an analog signal and a reference clock signal. The analog signal is sampled at the frequency of the clock signal and provides a first k-bit digital signal. A delay circuit samples the first digital signal at one-half of the reference signal frequency in order to produce a second k-bit digital signal. A multiplier multiplies the first and second digital signals and gives a phase difference signal.
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