| 摘要 |
<p>A variable data rate receiver is provided which employs a novel phase locked loop (PLL) of the type employing a data detection loop (65-72, 81) and a tracking loop (59-63, 81). The data detection loop (upper) is initially not coupled (at 75) to the input of the voltage controlled oscillator (81) in the tracking loop (lower) of the PLL, but is separated by an electronic switch (75). A phase lock detection circuit (64) is provided which is coupled (at 68) to the data detection loop and to the tracking loop (at 63) for detecting the difference in the voltage error signals (e and es) in the data detection loop and the tracking loop. When this error signal (e) indicates that the tracking loop is locked on to the carrier signal the electronic switch (75) is closed completing the phase locked loop circuit after lock on of the carrier is achieved.</p> |
