| 摘要 |
The data transmission circuit gives speed-up based on using bit lines directly connected to the gates of output transistors during data transmission in dynamic RAM and gives large scale integration with common I/O lines. The circuit comprises bit lines BL, BL (65)(66) connected to a memory cell (51), transistors (61)(62)(63)(64) for data input, transistors (57)(58) for data output, transistors (53)(54)(59)(60) for separation of electric connection, a transistor (56) for electric discharge to make a voltage level applied to other channel an earth voltage level, a sense amplifier (55) for amplifying the voltage difference between the bit lines BL, BL (65)(66), a signal (CSL) for selecting a memory cell (51).
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