| 摘要 |
PROBLEM TO BE SOLVED: To allow an upper layer semiconductor device having a high-performance CMOS circuit to be layered on a base semiconductor device having a CMOS structure, and achieve high performance and low power consumption of a 3D-CMOS structure.SOLUTION: A layered semiconductor device comprises: a first complementary semiconductor device 100 in which a CMOS circuit and a wiring layer are formed on a semiconductor substrate 110; metal electrodes 141, 142 formed on the first complementary semiconductor device 100 together with the wiring layer; semiconductor layers 231, 232 which are formed on the metal electrodes 141, 142 via an insulation film 220 and isolated by an n-MOS region and a p-MOS region, respectively, and which are primarily composed of Ge; and a second complementary semiconductor device 200 constituted by forming an n-MOSFET on the semiconductor layer in the n-MOS region and forming a p-MOSFET on the semiconductor layer in the p-MOS region. |
