| 摘要 |
In the present invention, a logical block of an FPGA is configured by a serial communication unit, a serial communication control portion, an EEPROM controller, an abnormal signal processing portion, an LED controller, an operation mode controller, a DPRAM, a clutch signal input portion, a jig substrate input output portion, a RAM, a motor controller, a motor drive waveform generating portion, an RL (right and left) motor current F/B portion, a UD (up and down) motor current F/B portion, a potentiometer control portion, a thermistor control portion, an RL encoder control portion, a UD encoder control portion, and an FPGA block abnormality monitoring portion. |
