发明名称 |
CLOCK GLITCH DETECTION CIRCUIT |
摘要 |
In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges. |
申请公布号 |
US2014006841(A1) |
申请公布日期 |
2014.01.02 |
申请号 |
US201314015519 |
申请日期 |
2013.08.30 |
申请人 |
ROHLEDER MICHAEL;KOCH THOMAS;LITOVTCHENKO VLADIMIR;LUEDEKE THOMAS;FREESCALE SEMICONDUCTOR, INC. |
发明人 |
ROHLEDER MICHAEL;KOCH THOMAS;LITOVTCHENKO VLADIMIR;LUEDEKE THOMAS |
分类号 |
G06F1/04 |
主分类号 |
G06F1/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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