| 摘要 |
In an improved routing of local clock interconnects, an endpoint including a representation of a pin is selected. An original delay is calculated in a route segment that supplies a clock signal to the pin. When the original delay exceeds a delay threshold, a cross-link is added in the route such that the cross-link completes a non-tree sub-network including the segment. The non-tree sub-network is a part of a non-tree network of interconnects carrying the clock signal. A revised delay is calculated in the segment without using delay information corresponding to another non-tree sub-network. The non-tree sub-network is virtually manipulated such that the revised delay can be computed in the manner of computing delay of a tree network. The route is modified using the revised delay in the segment such that a clock skew at the pin is reduced. |
