发明名称 Semiconductor integrated circuit
摘要 An SSCG generating a center-spread modulated clock centering on a frequency obtained by multiplying an input reference clock frequency by a predetermined number is configured to include a phase comparator, a VCO, and a modulation circuit formed by a frequency divider and a division ratio modulation circuit. The division ratio modulation circuit supplies the frequency divider with a division ratio modulated above and below the predetermined multiplication number, and outputs a magnitude relationship involved as a spread direction identification signal. The diagnostic circuit includes a counter that counts the modulated clock and, based on the spread direction identification signal, performs counting operations during an up-spread or down-spread period. Based on the values counted for a predetermined period, the operating status of the SSCG is diagnosed for the presence or absence of a failure, for example.
申请公布号 US8618852(B2) 申请公布日期 2013.12.31
申请号 US201313783294 申请日期 2013.03.02
申请人 RENESAS ELECTRONICS CORPORATION 发明人 TAKI YOSHITAKA
分类号 H03L7/06 主分类号 H03L7/06
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