CLOCK GENERATING APPARATUS FOR PERFORMING BIT ERROR RATE MEASUREMENT

摘要

A clock generating apparatus for performing bit error rate measurement is provided to generate a clock signals having minute interval by maintaining the linearity of multiple phase clock signals. In a clock generating apparatus for performing bit error rate measurement, a phase detector(420) compares the phase of an internal clock signal(CLK int) with that of an external clock signal(CLK ext). The phase detector outputs a control signal corresponding to the phase difference to the clock generator(410). The clock generator outputs a first clock signal of which phase is delayed by delaying the external clock signal. The controllable delay line(430) is formed in the return path connecting the first clock signal output terminal and phase detector of the clock generator. The controllable delay line is activated in the rate of BITS errors test mode(BER test mode- Bit Error Test mode). The controllable delay line delays the first clock signal in response to the external control signal(CON sig) by the first interval.