发明名称 |
Clock control circuitry and methods of utilizing the clock control circuitry |
摘要 |
A design-for-test (DFT) circuitry is disclosed. The DFT circuitry includes a first multiplexer operable to transfer one of a clock signal or an inverted clock signal based on a clock polarity control signal. The DFT circuitry also includes a burst counter coupled to the first multiplexer. The burst counter is operable to output a signal at a first logic state for a predefined pulse count. The DFT circuitry also includes a second multiplexer that is operable to output one of the clock polarity control signal or the clock signal according to a signal output from the burst counter. The DFT circuitry may also include a third multiplexer that forwards control signals identifying the predefined pulse count to the burst counter from different sources such as an external pin, a programmable interconnect, and a memory element. |
申请公布号 |
US8621303(B1) |
申请公布日期 |
2013.12.31 |
申请号 |
US201213354706 |
申请日期 |
2012.01.20 |
申请人 |
KANTIPUDI KALYANA RAVINDRA;SHAH DHWANI;GHOSH DASTIDAR JAYABRATA;ALTERA CORPORATION |
发明人 |
KANTIPUDI KALYANA RAVINDRA;SHAH DHWANI;GHOSH DASTIDAR JAYABRATA |
分类号 |
G01R31/28 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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