发明名称 |
Integrated circuits and methods for forming the integrated circuits |
摘要 |
A method for forming an integrated circuit includes forming a first dielectric layer over a gate electrode of a transistor. An etch-stop layer is formed over the first dielectric layer. An opening is formed through the first dielectric layer and the etch-stop layer, exposing a source/drain (S/D) region of the transistor. A metal layer is formed in the opening, contacting the S/D region of the transistor. The metal layer has a surface that is at least partially substantially level with a first top surface of the etch-stop layer. A damascene structure is formed and coupled with the metal layer. |
申请公布号 |
US8617986(B2) |
申请公布日期 |
2013.12.31 |
申请号 |
US20100841321 |
申请日期 |
2010.07.22 |
申请人 |
LIANG MING-CHUNG;CHEN CHII-PING;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
LIANG MING-CHUNG;CHEN CHII-PING |
分类号 |
H01L21/44 |
主分类号 |
H01L21/44 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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