发明名称 BANDWIDTH LIMITING ON GENERATED PCIE PACKETS FROM DEBUG SOURCE
摘要 Method, circuit, and system for performing an operation for regulating bandwidth, the operation comprising receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus. The operation then transmits, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets. The operation then drops one or more of the received debug data packets at the memory, and maintains a count of the one or more dropped debug data packets. The operation then updates the predefined ratio based on the count, and uses the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets.
申请公布号 US2013346801(A1) 申请公布日期 2013.12.26
申请号 US201213528224 申请日期 2012.06.20
申请人 FREKING RONALD E.;MCGLONE ELIZABETH A.;SPACH DANIEL R.;WOLLBRINK CURTIS C.;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 FREKING RONALD E.;MCGLONE ELIZABETH A.;SPACH DANIEL R.;WOLLBRINK CURTIS C.
分类号 G06F11/28 主分类号 G06F11/28
代理机构 代理人
主权项
地址