发明名称 Methods for manufacturing integrated circuit devices having features with reduced edge curvature
摘要 A structure, such as an integrated circuit device, is described that includes a line of material with critical dimensions which vary within a distribution substantially less than that of a mask element, such as a patterned resist element, used in etching the line. Techniques are described for processing a line of crystalline phase material which has already been etched using the mask element, in a manner which straightens an etched sidewall surface of the line. The straightened sidewall surface does not carry the sidewall surface variations introduced by photolithographic processes, or other patterning processes, involved in forming the mask element and etching the line.
申请公布号 US8609550(B2) 申请公布日期 2013.12.17
申请号 US201213350523 申请日期 2012.01.13
申请人 MOROZ VICTOR;BOMHOLT LARS;SYNOPSYS, INC. 发明人 MOROZ VICTOR;BOMHOLT LARS
分类号 H01L21/302 主分类号 H01L21/302
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