发明名称 |
DOWN-SAMPLING CLOCK AND DATA RECOVERY CIRCUIT HAVING SELECTABLE RATE AND PHASE OUTPUT AND METHOD OF OPERATION THEREOF |
摘要 |
A clock and data recovery (CDR) circuit, a method of recovering a clock and data from a received raw data stream and a BI-PON optical network transceiver (ONT) receiver front-end incorporating the CDR circuit. In one embodiment, the CDR circuit includes: (1) a line rate CDR circuit having a voltage controlled oscillator, the line rate CDR circuit configured to recover a raw data stream at a receiving line rate, (2) a fixed-rate down-sampler coupled to the line rate CDR circuit and configured to down-sample the raw data stream based on a fixed-rate and (3) a variable-rate down-sampler coupled to the fixed-rate down-sampler and configured further to down-sample the raw data sample based on a variable-rate. |
申请公布号 |
US2013322885(A1) |
申请公布日期 |
2013.12.05 |
申请号 |
US201213486552 |
申请日期 |
2012.06.01 |
申请人 |
CHOW HUNGKEI;SUVAKOVIC DUSAN;VAN PRAET CHRISTOPHE;TORFS GUY;YIN XIN;LI ZHISHENG;ALCATEL-LUCENT USA, INC. |
发明人 |
CHOW HUNGKEI;SUVAKOVIC DUSAN;VAN PRAET CHRISTOPHE;TORFS GUY;YIN XIN;LI ZHISHENG |
分类号 |
H04L7/033 |
主分类号 |
H04L7/033 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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