发明名称 SEMICONDUCTOR MEMORY DEVICE HAVING LAYOUT AREA REDUCED
摘要 A metal supplying an N well voltage is provided in a first metal interconnection layer. The metal is electrically coupled to an active layer provided in an N well region by shared contacts so that the N well voltage is supplied to the N well region. A metal supplying a P well voltage is provided in a third metal interconnection layer. The metal supplying the N well voltage is formed using a metal in the first metal interconnection layer and thus does not require a piling region to the underlayer, and only a piling region to the underlayer of the metal for the P well voltage needs to be secured. Therefore, the length in the Y direction of a power feed cell can be reduced thereby reducing the layout area of the power feed cell.
申请公布号 KR101336405(B1) 申请公布日期 2013.12.04
申请号 KR20070045587 申请日期 2007.05.10
申请人 发明人
分类号 G11C11/41;H01L21/8238 主分类号 G11C11/41
代理机构 代理人
主权项
地址