发明名称 Phase locked loop with adaptive loop filter
摘要 A PLL including an adaptive loop filter. The PLL includes a feedback circuit which provides a feedback signal based on an output signal and a phase detector generating an adjust signal based on a frequency of the feedback signal compared with a reference frequency. A charge pump receives the adjust signal and provides a control voltage. The adaptive loop filter includes a capacitor and an adaptive resistance with a current control input. A VCO has an output providing the output signal based on a voltage level of the control voltage. A bias generator converts the control voltage to a loop bias current, and has a bias output based on the loop bias current coupled to the current control input of the adaptive resistance. The bias output of the bias generator may also be used to control the charge current and the VCO using currents proportional to the loop bias current.
申请公布号 US8598955(B2) 申请公布日期 2013.12.03
申请号 US201213435089 申请日期 2012.03.30
申请人 XUE DASHUN;FREESCALE SEMICONDUCTOR, INC. 发明人 XUE DASHUN
分类号 H03L7/00 主分类号 H03L7/00
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