| 摘要 |
A semiconductor memory device comprises an all-bank selection signal generation unit which generates an all-bank selection signal by transmitting a level signal including information on a bank where refresh is performed in response to an all-bank refresh command; and a bank unit which includes multiple banks where refresh is performed in response to the all-bank selection signal or refresh is performed in response to an enabled per-bank selection signal when the level signal is enabled. [Reference numerals] (41) First pulse signal generation unit;(42) Bank selection unit;(51) Second pulse signal generation unit;(52) Signal delivery unit;(60) Address generation unit;(71) First bank;(72) Second bank;(73) Third bank;(74) Fourth bank |
