发明名称
摘要 <p>A method of performing vector operations on a semiconductor chip is described. The method includes performing a first vector instruction with a vector functional unit implemented on the semiconductor chip and performing a second vector instruction with the vector functional unit. The first vector instruction is a vector multiply add instruction. The second vector instruction is a vector leading zeros count instruction.</p>
申请公布号 JP2013543173(A) 申请公布日期 2013.11.28
申请号 JP20130530340 申请日期 2011.09.23
申请人 发明人
分类号 G06F17/16;G06F7/00;G06F9/30;G06F9/38 主分类号 G06F17/16
代理机构 代理人
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