发明名称 |
Sampling clock selection module of serial data stream |
摘要 |
A sampling clock selection module for a serial data stream is disclosed. The sampling clock selection module includes a multi-phase generation circuit, a sampling circuit, a comparison unit and a logic operation unit. The multi-phase generation circuit generates a plurality of non-overlapping clock phases derived from a reference clock signal. The phase selection circuit selects a sampling clock phase under a calibration mode. The sampling circuit performs sampling on the serial data stream a plurality of times to generate a plurality of sampled values in response to the sampling clock phase. The comparison unit compares the sampled values with the serial data stream so as to update a plurality of flag signals. The logic operation unit performs a logic operation on the flag signals so as to select a sampling clock phase under a normal operation mode from the clock phases.
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申请公布号 |
US8594263(B2) |
申请公布日期 |
2013.11.26 |
申请号 |
US201213448677 |
申请日期 |
2012.04.17 |
申请人 |
HUANG REN-FENG;MIAO HUI WEN;TSO KO-YANG;CHAO CHIN-CHIEH;RAYDLUM SEMICONDUCTOR CORPORATION |
发明人 |
HUANG REN-FENG;MIAO HUI WEN;TSO KO-YANG;CHAO CHIN-CHIEH |
分类号 |
H04L7/00 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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