METHOD BASED ON STANDARD CMOS IC PROCESS FOR MANUFACTURING COMPLEMENTARY TUNNELING FIELD-EFFECT TRANSISTOR

摘要

The present invention relates to the field of field-effect transistor logic devices and circuits in CMOS ultra large-scale integration circuit (ULSI). Provided is a method utilizing a standard CMOS IC process for manufacturing a complementary tunneling field-effect transistor. The method utilizes complementary P-well and N-well masks in the standard COMIS IC process for injection-forming of wells, for channel doping, and for threshold adjustment to implement an intrinsic channel and body area of a tunneling field-effect transistor (TFET), and utilizes a spacing between a gate and a drain on a mask pattern for suppression of a bipolar effect of the TFET to implement a complementary TFET. The present invention employs an existing process in the standard CMOS IC process, and implements the manufacturing of the complementary TFET without any additional mask or step in the process.