摘要 |
It is desired to effectively suppress breaking of a protection target circuit caused by direct application of an ESD surge voltage to the circuit. The semiconductor device includes: a VDD pad; a signal output pad; a GND pad; a high-potential power source line; a signal line; a low-potential power source line; main ESD protection elements; a PMOS transistor; and an output circuit. The output circuit includes: an NMOS transistor N<b>1</b>whose source is connected to the signal line, and whose drain is connected to the low-potential power source line; and an NMOS transistor N<b>2</b>connected between the gate of the NMOS transistor N<b>1</b>and the low-potential power source line. The source of the PMOS transistor is connected to the signal line, the drain thereof is connected to the gate of the NMOS transistor N<b>1</b>, and the gate and back gate thereof are connected to the high-potential power source line. |